In order to achieve higher circuit speed and density in integrated circuit field effect transistors, it is necessary to reduce both the horizontal and the vertical dimensions of the device. Experimental and analytical evidence indicates that the threshold voltage, V.sub.T, of IGFET's falls sharply as the source-drain spacing is reduced. Studies for example by F. H. De La Moneda, "Threshold Voltage from Numerical Solution of the Two Dimensional MOS Transistor", IEEE Transaction on Circuit Theory, Vol. CT-20, pages 666-673, Nov. 1973, show that in order to avoid this drop, it is necessary to compensate by scaling down both the horizontal and the vertical dimensions of the device for example by reducing the thickness of the gate oxide and the junction depth and, in addition, by scaling up the substrate doping level by some factor. However, reductions in gate oxide thickness and increased substrate doping have adverse side effects. It is well known that reduced oxide thicknesses diminish the reliability of the device. The threshold voltage and the junction capacitance increase with the square root of the doping concentration and therefore devices with increased doping concentration become impractical for faster circuit applications. In view of this, it is necessary to use high resistivity substrates for the formation of the smaller IGFET device and then later adjust the device parameters to reduce the detrimental influence of a high resistivity substrate on the threshold voltage. Such adjustments include ion implantation of the substrate, reduction of the oxide thickness, and reduction of the junction depth to the extent that such reduction is possible with conventional device fabrication processes. Conventional processes for fabricating insulated gate field effect transistors determine the junction depth by the initial drive-in cycle and subsequent heat cycles associated with oxidation steps. These conventional device fabrication processes are not capable of producing very shallow source and drain junctions necessary for IGFET's of reduced size.